•   Phone: 919-901-888224   Email: divyaprabha@ssit.edu.in
    Designation : Associate Professor
    Qualification : M.S
    Experience: 19 Years
    Birthdate: 26/06/1974
    Interests: signals, DSP, VHDL
    Address: "Shreyas Nilaya" 2nd Cross
      Channabasaveshwara Layout,
  • Qualifications

     Course  Specialization  Board / University  Year
     MS  Software Systems  Bits Pilani  1999
     BE  Electronics and Communication  Bangalore University  1996

    Basic March-C Algorithm based BIST for Embedded Memories in FPGA
    Published on 18/05/2016
    at International Conference , VVIET Mysore

    FPGA Implementation of Area Efficient Block LMS Algorithm
    Published on 03/05/2012
    at International Conference, DSCE,Bangalore

    Generalized De Brujin Graph Implementation for massive NoCs,
    Published on 30/04/2013
    at ICRTET-2013, Bangalore

    Implementation of Adaptive Router for Networks-On-Chip on FPGA using Buffer Resize Technique
    Published on 28/06/2013
    at International Conference, Dr AIT,Bangalore

    Modified March-C Algorithm based BIST
    Published on 03/07/2016
    at International Conference, ICRMET, Tirupati

    Optimization of BCD Adder using Reversible logic based on FPGA
    Published on 14/07/2017
    at International Conference , VVIET Mysore

    Survey on Dynamic Buffer Resize Technique for Networks on Chip on FPGA.
    Published on 23/03/2013
    at National Conference , Shridevi Institute of Engineering and technology, Tumkur